1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a ZQ calibration circuit for adjusting impedance of an output circuit and a semiconductor device having such a ZQ calibration circuit.
2. Description of the Related Art
The speed of recent electronic systems has been enhanced, and an extremely high data transfer rate has been achieved between semiconductor devices forming a system. In order to achieve such an ultrafast data transfer, the amplitude of data signals is reduced. Further, impedance of a transmission line between semiconductor devices and an output impedance of an output circuit of the semiconductor device are matched with each other. The matched impedance provides transmission without causing distortion to data signals having a small amplitude, thereby enhancing a data transfer rate. If the impedance of the transmission lines between the semiconductor devices and the output impedance of the semiconductor device are not matched with each other, then a data waveform is dulled during transmission so as to cause an overshoot or an undershoot, so that a high speed data transfer cannot be performed.
In order to match impedance of a transmission line and output impedance of an output circuit with each other, it is necessary to adjust the output impedance of the semiconductor device so as to match the impedance of the transmission line. Generally, a calibration circuit is used to adjust output impedance of a semiconductor device. For example, a ZQ pin is provided as a ZQ calibration terminal in a semiconductor device, and an external ZQ calibration command (ZQCS or ZQCL) is inputted into the ZQ pin. When the external ZQ calibration command (ZQCS or ZQCL) is inputted, a ZQ calibration operation is performed within a period defined by the command. During the ZQ calibration operation, the output circuit cannot be used. Accordingly, access to chips is prohibited, and a next command is not inputted. Thus, the period defined by the ZQ calibration command is for ZQ calibration. The ZQ calibration should be completed within this period.
The period for ZQ calibration is defined as follows:
ti tZQinit=512*tCK tZQCS=64*tCK tZQoper=256*tCK Here, tCK represents a cycle of a clock. These specifications are defined by the number of clocks. Specifically, in the AC specifications, a ZQ calibration period (tZQinit) for ZQ calibration performed during an initial stage after power is turned on is defined as tZQinit=512*tCK. Further, ZQ calibration periods for ZQ calibration performed after the initial stage are defined according to inputted commands. A ZQ calibration period (tZQCS) for ZQ calibration performed when an external ZQ calibration command of ZQCS is inputted is defined as tZQCS=64*tCK. A ZQ calibration period (tZQoper) for ZQ calibration performed when an external ZQ calibration command of ZQCL is inputted is defined as tZQoper=256*tCK.
When power is turned on, impedance adjustment can be performed for a long period of time. The ZQ calibration periods after the initial stage are short (64*tCK, 256*tCK). This is because the impedance adjusted by the intitial ZQ calibration is used for the subsequent ZQ calibrations and thereby the subsequent ZQ calibrations can be completed within a shorter period of time. Further, since the subsequent ZQ calibration periods are short, it is possible to shorten a period during which chip access is prohibited. It is assumed that the short-time ZQ calibrations (tZQCS, tZQoper) are performed at a certain frequency. When a short-time ZQ calibration is performed in a state in which device variation is small, specifically in cooperation with refresh cycles, it is possible to perform the ZQ calibration (tZQCS) without lowering the performance of the semiconductor device.
However, the impedance varies according to conditions under which the device is placed, such as an operation mode, a power source voltage, and temperature. That is, in a case where a self-refresh operation or the like is performed for a long period of time, even if a short-time ZQ calibration (tZQCS or tZQoper) is performed after the self-refresh operation, there is no guarantee that the impedance can be adjusted. As shown in FIG. 1, even if a DLL lock period (tDLLK=512*tCK) after completion of a self-refresh operation is employed for a ZQ calibration, there is no guarantee that the impedance can be adjusted. In accordance with the AC specifications, i.e., when a short-time ZQ calibration (tZQCS or tZQoper) is performed after a ZQ calibration command has been inputted, there is little possibility that the impedance can be adjusted.
A ZQ calibration operation is completed in a short period of time if the ZQ calibration result is close (or equal) to an output impedance at the time when a ZQ calibration command was inputted. If there is a difference between the impedance and the ZQ calibration result, then the ZQ calibration operation may not be completed within the defined ZQ calibration period. If the impedance matching is not completed successfully, the impedance of the transmission line does not match the output impedance of the semiconductor device. In this case, a data waveform is dulled during transmission so as to cause an overshoot or an undershoot, so that a high speed data transfer cannot be performed.
The following references relate to a ZQ calibration operation and a refresh operation of a semiconductor memory. Patent Document 1 (Japanese laid-open patent publication No. 2002-026712) discloses that a slew rate of an output circuit is adjusted by matching an external terminator. Patent Document 2 (Japanese laid-open patent publication No. 08-335871) discloses that a switching transistor is turned on and off by an external control signal so as to adjust the impedance. Patent Document 3 (Japanese laid-open patent publication No. 2005-065249) discloses that a terminating resistance of an input terminal and an impedance of an output circuit are adjusted by using one external resistance. Patent Document 4 (published Japanese translation No. 2005-506647) discloses that an input buffer is set in a disable state during an automatic refresh operation and in a low-power pre-charged state after the automatic refresh operation to thereby reduce a power of a semiconductor memory.
If there is a difference between a ZQ calibration result and an output impedance at the time when a ZQ calibration command was inputted, then the ZQ calibration operation may not be completed within the defined ZQ calibration period. In this case, the impedance of the transmission line does not match the output impedance of the semiconductor device. As a result, a data waveform is dulled during transmission so as to cause an overshoot or an undershoot, so that a high speed data transfer cannot be performed. The aforementioned references do not consider these problems and are silent on these problems.